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Electrostatic discharge (ESD) protection is required for all integrated circuits (ICs) against ESD failures. For decades, on-chip ESD protection relies on PN-junction-based active device structures inside Si for ESD discharge, which inherently has ESD-induced parasitic effects, including capacitance, leakage, and noise, which seriously affect IC performance. Addressing the ESD design overhead is an emerging challenge for ICs at advanced technology nodes. Recently, a non-traditional graphene nano-electromechanical-system (NEMS) ESD protection structure has been explored as an alternative low-parasitic ESD protection solution for advanced ICs, which is an above-IC mechanical switch that has the potential to dramatically reduce the ESD design overhead inherent to any in-Si ESD protection structures. Benefited from its unique materials properties, graphene was also studied as interconnects for on-chip ESD protection, possibly replacing traditional metal interconnects for ICs. This paper provides an overview of recent advances in developing graphene-based on-chip ESD protection for future ICs. Statistic studies show excellent ESD protection capability of graphene NEMS (gNEMS) ESD switches, i.e., >1.5KV/µm2, and graphene ESD interconnects, i.e., ~108 A/cm2, suggesting a potential paradigm change in on-chip ESD protection for future chips. The outlook for graphene-based ESD protection will be discussed too.